Generally, in a thin film transistor display, gates of respective thin film transistors TFTs in a pixel region are supplied gate driving signals by a gate driving circuit. The gate driving circuit can be integrated on an array substrate of a liquid crystal display through an array process, that is, gate driver on array GOA process, such that cost may be saved and a beautiful design with two symmetric sides may be achieved for the liquid crystal panel. Meanwhile, bonding area and fan-out wiring space for a gate driving integrated circuit may be omitted, such that a narrow frame design may be achieved.
With reference to FIG. 1, a GOA circuit in the prior art comprises a plurality of shift registers, each of the shift registers is configured to supply a gate scanning signal to a gate connected to an signal output terminal Output(n) of the shift register, supply a reset signal to an adjacent shift register prior thereto, and supply an input signal to an adjacent shift register next thereto.
FIG. 2a illustrates a schematic diagram of structure of a traditional shift register in the prior art. With reference to FIG. 2a, the shift register comprises an input unit 1, a reset unit 2, a driving control unit 3, a pulling-up unit 4 and a pulling-down unit 5. An input terminal of the input unit 1 is configured to receive an input signal Input, and an output terminal of the input unit 1 is connected to a first node A. An input terminal of the reset unit 2 is configured to receive a reset control signal Reset, and an output terminal of the reset unit 2 is connected to the first node A. A first terminal of the driving control unit 3 is connected to the first node A, and a second terminal of the driving control unit 3 is connected to a second node B. A first input terminal of the pulling-up unit 4 is connected to the first node A, a second input terminal of the pulling-up unit 4 is configured to receive a first clock signal CK, and an output terminal of the pulling-up unit 4 is connected to a driving signal output terminal Output of the shift register. A first input terminal of the pulling-down unit 5 is connected to the second node B, a second input terminal of the pulling-down unit 5 is connected to a reference signal terminal Vref, and an output terminal of the pulling-down unit 5 is connected to the driving signal output terminal Output of the shift register.
The input unit 1 is configured to set a level at the first node A to a high level (or a low level) under the control of the input signal Input, the reset unit 2 is configured to set the level at the first node A to a low level (or a high level) under the control of the reset control signal Reset, the driving control unit 3 is configured to set a level at the second node B to a low level (or a high level) when the first node A is at a high level (or a low level) and set the level at the first node A to a low level (or a high level) when the second node B is at a high level (or a low level), the pulling-up unit 4 is configured to supply the first clock signal CK to the driving signal output terminal Output when the first node A is at a high level (or a low level), the pulling-down unit 5 is configured to supply a signal at the reference signal terminal Vref to the driving signal output terminal Output when the second node B is at a high level (or a low level). In the above shift register, when an active pulse signal of the input signal is a high level signal (or a low level signal), the driving signal output terminal Output supplies a high level signal (or a low level signal) to a gate line corresponding thereto, and thin film transistors connected to the gate line are all turned on.
It is well-known that a liquid crystal display screen will be turned to black slowly after being powered off due to charge accumulation in the liquid crystal display screen, which has a negative effect on quality of the liquid crystal display screen. Therefore, in order to solve the above problem, in the prior art, a discharging control unit is commonly added in the shift register. As shown in FIG. 2b, a control terminal of the discharging control unit 6 is configured to receive a discharging control signal EN1, an input terminal of the discharging control unit 6 is connected to the reference signal terminal Vref, a first output terminal of the discharging control unit 6 is connected to the second node B, and a second output terminal of the discharging control unit 6 is connected to the driving signal output terminal Output. The discharging control unit 6 is configured to output a low level signal (or a high level signal) to the second node B and output a high level signal (or a low level signal) to the driving signal output terminal Output under the control of the discharging control signal EN1 during the period that the liquid crystal display screen is powered off, such that the shift register can pull up (or pull down) the level at the driving signal output terminal Output through the discharging control unit 6 during the period that the liquid crystal display screen is powered off, and thus the thin film transistors connected to the gate line corresponding to the shift register can be turned on, which enabling rapid releasing of the accumulated charges in the liquid crystal display screen.
However, in the above shift register, although the discharging control unit outputs a low level signal (or a high level signal) to the second node and outputs a high level signal (or a low level signal) to the driving signal output terminal during the period that the liquid crystal display screen is powered off, the pulling-up unit might be controlled by the first node to output the first clock signal to the driving signal output terminal and the pulling-down unit might be controlled by the second node to output the signal at the reference signal terminal to the driving signal output terminal since the pulling-up unit and the pulling-down unit are generally constituted by thin film transistors through which leakage currents may flow, such that the level at the driving signal output terminal cannot be fully pulled up (or pulled down), and thus charges accumulated in the liquid crystal display screen cannot be released rapidly.